Static random access memory (SRAM) is a type of RAM that uses transistor driven memory cells to latch bits of data for memory storage and is used in a large variety of consumer electronics, such as computers and cellular telephones. Memory cells in an SRAM circuit are typically arranged in an array, such that the SRAM includes individually addressable rows and columns to which data can be written and from which data can be read. The individually addressable rows and columns are controlled by peripheral circuitry that receives decoded signals corresponding to memory locations, which could be generated from a processor, such that the peripheral circuitry determines which of the memory cells in the array are accessed for read and write operations at any given time. Typically, during a read operation, an accessed memory row outputs its data content onto complementary pairs of column bit lines, with the data content of each of the complementary pair of column bit lines being switched to a complementary bit-level read output of a column multiplexer. The complementary bit-level read output is input to a differential sense amplifier for a determination of the data value.
Typical SRAM memory arrays are optimized for a large number of memory rows. However, in applications better suited for smaller memory arrays, a differential amplifier can become impractical due to its large size. In smaller memory arrays, it may be more area efficient to use gate type sense circuits instead of a differential amplifier. However, a gate-type sense circuit limits the array to a smaller number of memory rows (e.g., 8-32 memory rows) in order to achieve performance. The memory array could be partitioned in multiple banks having 8-32 rows, with each bank having a gate-type sense circuit. However, too many banks of rows defeats the purpose of reducing the size of the memory array. Hence, the gate type sense approach is typically used for relatively small memory arrays only. In addition, in a memory array having a low number of memory rows, a column multiplexer can apply an undesirable load on the column bit lines, such that the speed of the SRAM memory array can be reduced.